1. Field of the Invention
This invention relates to an amplifier circuit that has a level shift function.
2. Description of the Related Art
Semiconductor integrated circuits move to finer design rules and a lower power supply voltage. In some cases, however, they are required to operate at a power supply voltage higher than a certain voltage. For example, a semiconductor integrated circuit used for audio signal processing has a signal processing-associated circuit that operates being provided with a low power supply voltage and an output-associated circuit that operates being provided with a higher power supply voltage. In such a case, there is a need to shift a DC level of a signal outputted from the signal processing-associated circuit so as to adjust to a DC level of the output-associated circuit as well as a need to amplify and output the shifted signal in the output-associated circuit.
An outline structure of a conventional semiconductor integrated circuit used in the audio signal processing is described hereafter referring to FIG. 2. The semiconductor integrated circuit shown in FIG. 2 has a signal processing-associated circuit 100 that operates being provided with a first power supply voltage VDDL and an output-associated circuit 101 that operates being provided with a second power supply voltage VDDH that is higher than the first power supply voltage VDDL.
A level shift circuit 102 is provided in a rear stage of the signal processing-associated circuit 100. The level shift circuit 102 changes a DC level of an input signal Vin supplied from an input terminal 103 without changing its amplitude, and is composed of components including an operational amplifier and a plurality of resistors. For more details, refer to FIG. 1 of Japanese Patent Application Publication No. 2001-244760, for example.
When the input signal Vin has amplitude centered around a voltage VREFL, the voltage VREFL is usually set at a half of VDDL in order to secure a maximum dynamic range. Thus, the input signal Vin can swing to its maximum amplitude making a half of VDDL a center of the amplitude.
The output-associated circuit 101 is provided with a resistor 104, a resistor 105 and an operational amplifier 106. A signal outputted from the level shift circuit 102 is applied to a first differential input terminal (−) of the operational amplifier 106 through the resistor 104, while a voltage VREFH is applied to a second differential input terminal (+) of the operational amplifier 106. An output of the operational amplifier 106 is outputted from an output terminal 107 to a circuit such as a speaker (not shown) in a subsequent stage, as well as being applied to the first differential input terminal (−) through the resistor 105 that serves as a feedback resistor.
When an output signal Vout has amplitude centered around the voltage VREFH, the voltage VREFH is usually set at a half of VDDH because of the same reason as described above regarding the input signal Vin. Thus, the output signal Vout can swing to its maximum amplitude making a half of VDDH a center of the amplitude.
Next, the output signal Vout will be described using the voltage VREFH, a resistance R1 of the resistor 104, a resistance R2 of the resistor 105 and the like.
The DC level of the input signal Vin is shifted by (VREFH−VREFL) by the level shift circuit 102. Therefore, when a voltage supplied to the first differential input terminal (−) of the operational amplifier 106 is denoted by V1, V1 is represented by the following equation 1:
                              V          ⁢                                          ⁢          1                =                                            R              ⁢                                                          ⁢              1              ⁢              Vout                        +                          R              ⁢                                                          ⁢              2              ⁢                              (                                  Vin                  +                  VREFH                  -                  VREFL                                )                                                                        R              ⁢                                                          ⁢              1                        +                          R              ⁢                                                          ⁢              2                                                          [                  Equation          ⁢                                          ⁢          1                ]            
Here, the input signal Vin is represented by the following equation 2:Vin=VREFL+vi  [Equation 2]where vi is a change in the input voltage Vin. Therefore, the equation 1 turns into the following equation 3:
                              V          ⁢                                          ⁢          1                =                                            R              ⁢                                                          ⁢              1              ⁢              Vout                        +                          R              ⁢                                                          ⁢              2              ⁢                              (                                  vi                  +                  VREFH                                )                                                                        R              ⁢                                                          ⁢              1                        +                          R              ⁢                                                          ⁢              2                                                          [                  Equation          ⁢                                          ⁢          3                ]            
On the other hand, when a voltage supplied to the second differential input terminal (+) of the operational amplifier 106 is denoted by V2, V2 is represented by the following equation 4, as described above:V2=VREFH  [Equation 4]
Since a difference between the two differential input voltages to the operational amplifier 106 is ideally zero, V1 is equal to V2. Combining the equation 3 with the equation 4 derives the following equation 5 which represents the output voltage Vout:
                    Vout        =                                                            R                ⁢                                                                  ⁢                2                                            R                ⁢                                                                  ⁢                1                                      ⁢            vi                    +          VREFH                                    [                  Equation          ⁢                                          ⁢          5                ]            
However, there are problems with the conventional structure shown in FIG. 2. The problems are an error in the gain and a DC offset voltage caused by variations in the level shift operation of the level shift circuit 102.
In order to reduce a size and power consumption of the semiconductor integrated circuit, it is required that the level shift operation and the amplification as described above are implemented with as small circuit area as possible and with low power consumption.
This invention intends to offer an amplifier circuit that is less likely to cause the error in the gain and the DC offset voltage and is suitable for reducing the size and the power consumption.